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Phoenix Camera Link Framegrabber (D24-PE1)

Artikelnummer: AS-PHX-D24CL-PE1

  • Base Camera Link Configuration.
  • Single lane (x1) v1.1 PCI Express interface.
  • PCI Express burst rates in excess of 190Mbytes/sec.
  • Supports Power over Camera Link with SafePower.
  • Multi-tap & multi-channel camera formats, incl. line and pixel interleaved.
  • Maximum pixel clock of 85MHz.
  • SDK supports various operating systems.
  • v1.2 Camera Link compliant.
  • Hardware control of scatter-gather requiring 0% CPU.
  • Serial port with EIA-644 signalling, also accessible as a standard Windows COM port.
  • Supports Camera Link serial comms API.
  • Implements Data Valid (DVAL) for slow data rate cameras.
  • Opto-Isolated, TTL and EIA-644 I/O.
  • Utilises software configurable FPGA technology.
  • Common API allows seamless migration for existing Phoenix PCI users.
  • RoHS compliant.

Phoenix-D24CL is a PCI Express board for the acquisition of digital data from a variety of Camera Link sources, including digital frame capture and line scan cameras. It supports all the formats of Base configuration, i.e. single 8 to 16 bit data, through 8 bit RGB, to dual tap 12 bit sources.

Phoenix-D24CL also supports various camera tap formats, such as line interlaced – adjacent lines are output simultaneously; line offset – lines are output from different parts of the CCD simultaneously; pixel interlaced – adjacent pixels on the same line are output simultaneously; and pixel offset – pixels are output from different parts of the same line simultaneously.

Phoenix-D24CL supports the Power over Camera Link (PoCL) functionality with SafePower and is able to provide power to PoCL enabled cameras via the Camera Link data cable thereby removing the need for a separate power supply. Conventional non-PoCL cameras are still supported.

ROI and sub-sampling controls are used to increase application processing speed by only storing the required data. In addition the LUT functionality provides support for gamma correction, dynamic range cropping, binary thresholding and Bayer white color balancing in real time. The DataMapper further reduces the load on the host processor by mapping and packing the acquired data prior to transfer across the PCI Express bus. For example, the acquired data can be mapped into a suitable format and transferred directly to the graphics display, without the need for any host processing.

The PCI interface comprises intelligent scatter-gather hardware which reads its instructions direct from memory without any host CPU intervention. This in turn controls the DMA engine, which transfers the packed video data into any target memory which can be reached from the PCI Express bus. This can be system memory, graphics memory, or even other devices on the same or other PCI busses, such as DSP cards, etc.

The majority of the functionality is implemented in a single FPGA (Field Programmable Gate Array) providing a flexible solution for interfacing to Camera Link compliant sources. The FPGA implements the PCI Express interface, hardware scatter-gather control of DMA, Acquisition Control, Region of Interest (ROI) and sub-sampling control, DataMapping functions, Datapath FIFOs and Counter/Timer support. In addition the board contains Look Up Table

(LUT) functionality, a Universal Asynchronous Receiver Transmitter (UART), 4 bit opto-isolated I/O, two 2 bit differential input ports and two 8 bit TTL I/O ports.

The PHX Software Development Kit (SDK), available as a separate item, allows rapid system development and integration. It provides comprehensive example applications and optimized libraries, and is available for a variety of operating systems via a common API, including 32 bit and 64-bit Windows and Linux as well as Mac OS X, DOS and QNX. Drivers for third party applications are also available, e.g. Common Vision Blox, Cognex VisionPro, LabVIEW, etc. As well as functions that control the hardware, the libraries include general purpose functions for the manipulation and display of images. A separate datasheet describes the SDK in detail.