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Phoenix LVDS Frame Grabber (PE4)

Part-Number: AS-PHX-D36-PE4

  • 36 bit EIA-644 (LVDS) data, 4 bits for control.
  • 4 lane v1.1 PCI Express interface.
  • PCIe burst rates in excess of 750Mbytes/sec.
  • Supports digital areascan / linescan cameras.
  • Multi-tap & multi-channel camera formats, incl. line and pixel interleaved.
  • Maximum pixel clock of 75MHz.
  • PHX SDK supports various operating systems.
  • Bus mastering hardware control requires 0% CPU.
  • Dual channel serial port with both EIA-232 & EIA-644 signalling.
  • Opto-Isolated, TTL and EIA-644 I/O.
  • Utilises software configurable FPGA technology.
  • Common API allows seamless migration for existing Phoenix PCI users.
  • RoHS compliant.

Phoenix-D36 is a PCI Express board for the acquisition of digital data from a variety of sources, including digital frame capture and line scan cameras. It has 36 bits used for input data, with 4 bits for control. This provides support for a single 12 bit RGB or 32 bit mono data source, including multi-tap cameras. The 4 bit control inputs are dedicated as Frame Enable, Line Enable, Data Enable and Pixel Clock. Alternatively four of the data inputs can be re-assigned as an additional control port, thus allowing two independent 16 bit mono cameras to be supported. Data widths up to the above maximums are also handled, i.e. 8, 10 or 12 bit RGB and 8, 10, 12, 14, 16 or 32 bit mono.

Phoenix-D36 also supports various camera tap formats, such as line interlaced – adjacent lines are output simultaneously; line offset – lines are output from different parts of the CCD simultaneously; pixel interlaced – adjacent pixels on the same line are output simultaneously; and pixel offset – pixels are output from different parts of the same line simultaneously.

ROI and sub-sampling controls are used to increase application processing speed by only storing the required data. In addition the LUT functionality provides support for gamma correction, dynamic range cropping and binary thresholding in real time. The DataMapper further reduces the load on the host processor by mapping and packing the acquired data prior to transfer across the PCI Express bus. For example, the acquired data can be mapped into a suitable format and transferred directly to the graphics display, without the need for any host processing.

The PCI interface comprises intelligent scatter-gather hardware which reads its instructions direct from memory without any host CPU intervention. This in turn controls the DMA engine, which transfers the packed video data into any target memory which can be reached from the PCI Express bus. This can be system memory, graphics memory, or even other devices on the same or other PCI busses, such as DSP cards, etc.

The majority of the functionality is implemented in a single FPGA (Field Programmable Gate Array) providing a flexible solution for interfacing to digital sources. The FPGA implements the PCI Express interface, hardware scatter-gather control of DMA, Acquisition Control, Region of Interest (ROI) and sub-sampling control, DataMapping functions, Datapath FIFOs, and Counter/Timer support. In addition the board contains Look Up Table (LUT) functionality, a dual Universal Asynchronous Receiver Transmitter (UART) with support for EIA-232 (RS-232) and EIA-644 (LVDS) levels, 4 bit opto-isolated I/O, two 2 bit differential input ports and two 8 bit TTL I/O ports.

The PHX Software Development Kit (SDK), available as a separate item, allows rapid system development and integration. It provides comprehensive example applications and optimized libraries, and is available for a variety of operating systems via a common API, including 32 bit and 64-bit versions of Windows and Linux as well as QNX. Drivers for third party applications are also available, e.g. Common Vision Blox, Cognex VisionPro, StreamPix, LabVIEW, MATLAB etc. As well as functions that control the hardware, the libraries include general purpose functions for the manipulation and display of images. A separate datasheet describes the SDK in detail.